VLSI Circuit Crafting: Essential Skills in Physical Design

Why Choose Garranto Academy for Your VLSI Circuit Crafting: Essential Skills in Physical Design Training?

VLSI Circuit Crafting training to access cutting-edge content, industry experts, and hands-on learning experiences, empowering you to navigate and excel in the dynamic field of VLSI physical design.

Course Overview:

The "VLSI Circuit Crafting: Essential Skills in Physical Design" is a 3-day program designed to equip participants with in-depth knowledge and practical skills in VLSI physical design. This course covers essential aspects of semiconductor history, VLSI circuits, CMOS vs FinFet technologies, IC design flow, and explores critical concepts in floorplanning, power planning, placement, clock tree synthesis, routing, static timing analysis, and physical verification.

What You'll Learn in Our VLSI Circuit Crafting: Essential Skills in Physical Design Certification Course?

Course Objectives:

• Understand the fundamental concepts of the Physical design process such as floorplanning, placement, clock tree synthesis, and routing.
• Analyze physical design problems and employ appropriate automation algorithms for placement, floorplanning, and routing.
• The course extensively covers the entire physical design flow including physical verification and basic concepts of power analysis.
• Gain complete exposure to various technologies and methodologies used in physical design.

Prerequisites:

• Digital Electronics Knowledge: Participants should have a foundational understanding of digital electronics, including basic principles and concepts.
• Basics of ASIC Design: Familiarity with the fundamentals of ASIC design is essential for effective engagement with the course content.

Course Outline:

Module 1: Introduction to VLSI Physical Design

• History of semiconductors
• VLSI circuits and application, CMOS vs FinFet
• IC Design flow, Physical Design, Risks and Terminologies, Impact

Module 2: Floorplanning (part -1)

• Goals, Inputs, Output and steps in floor planning, Technology LEF
• Aspect Ratio, Core utilization, Core rows
• Macro placement, Blockages, Physical cells

Module 3: Floorplanning (part -2)

• Core and Module sizes, Cell utilization
• Target utilization, Effective utilization
• Halo, Die size reduction techniques.

Module 4: Power planning (part -1)

• Purpose/Goals and types of power planning, Global net connection
• Core rings, Block rings, Power stripes

Module 5: Power planning (part -2)

• Power routing, Special Route
• Power via generation

Module 6: Placement (part – 1)

• Objectives, Inputs, Checks before placement, placement rows.
• Steps of placement, JTAGs, Spare cells, Congestion
• Placement blockages, placement optimization

Module 7: Placement (part – 2)

• Checks after placement, Debugging placement.
• Scan chains, scan reordering
• Scan def usage

Module 8: Clock Tree Synthesis (CTS)

• Terminologies, Objectives, and Checks before CTS
• Inputs, Outputs and Effects of CTS, NDR
• Clock buffers and clock inverters, Post CTS optimization

Module 9: Routing

• Goals, Pre-route checks, Inputs, and outputs
• Routing order, Routing grids/tracks, Stages of routing, single cut, multi-cut via
• Post-route optimization, Signal integrity, Routing algorithm

Module 10: Static Timing Analysis

• Inputs, Outputs, Clock, Setup and hold time, Clock skew.
• Transition time, required time, Arrival time, Setup slack, Hold slack.
• Timing exceptions, Timing path, Types of timing path
• Setup and Hold violations, Useful skew.

Module 11: Physical Verification and Engineering Change Orders (ECO)

• DRC, LVS, well taps, wire gaps
• ERC, Antenna, LEC, XOR
• Purpose and process of ECOs

Module 12: challenges in advanced nodes

• Double pattern technology, Colorizing cells
• Colour aware placement, Colour-aware routing
• GDS stream out mapfile.

Course Outcomes:

By the end of this course, participants will:

• Be able to start a career in the VLSI industry as a Physical Design engineer.
• Understand the entire physical design flow from floorplanning, power planning, placement, clock tree synthesis, and routing.
• Learn the efficient techniques of timing analysis and signoff checks.
• Be able to know how to place the blocks and how to partition the blocks while designing the layout for IC.
• Understand the concept of logic optimization in placement, clock tree synthesis, and routing.

Key Benefits of Embracing VLSI Circuit Crafting: Essential Skills in Physical Design

Cultivate expertise in VLSI circuit design with our program, mastering essential skills in physical design for efficient chip development and cutting-edge electronic systems.

How VLSI Circuit Crafting: Essential Skills in Physical Design Can Revolutionize Your Chip Development Skills?

Experience a revolutionary enhancement in your chip development skills as VLSI Circuit Crafting transforms your understanding of physical design, fostering efficiency and innovation in electronic systems.